1. Field of the Invention
The present invention relates to an InP heterojunction field effect transistor structure.
2. Related Background Art
An n-InP/InGaAs heterojunction structure, an n-AlInAs/InGaAs heterojunction structure, and an n-AlInAs/InP heterojunction structure are known as an InP heterojunction field effect transistor.
For example, such a transistor is described in "High-Performance InAlAs/InGaAs HEMT's and MESFET's, IEEE ELECTRON DEVICE LETTER, Vol. 9, No. 7, July 1988". InGaAs has a high mobility in a low electric field, but a low mobility in a high electric field due to polar optical scattering. For this reason, even if a field effect transistor (FET) having a short gate length is formed, good characteristics cannot be obtained in a high electric field. A transistor having an n-AlInAs/InP heterojunction structure has an InP channel with a high electron saturation rate even in a high electric field. However, this transistor has a low mobility in a low electric field, thus posing problems in terms of FET characteristics.
In order to solve these problems, an FET described in Japanese Patent Application No. 63-9192 filed by the present inventor is proposed. This FET has advantages of both the conventional transistors described above and has a structure shown in FIG. 1. An undoped InP layer 320, an undoped InGaAs layer 330, an n-InP layer 340, an undoped InP layer 350, and an n-AlInAs layer 360 are sequentially formed on a semi-insulating InP substrate 110. Source and drain electrodes 410 and 430 are formed in ohmic contact with the n-AlInAs layer 360. A gate electrode 420 which forms a Schottky junction between the source and drain electrodes is formed on the n-AlInAs layer 360.
An experiment was conducted using a transistor sample in which each of the n-InP layer 340 and the undoped InP layer 350 had a carrier concentration of 3.times.10.sup.17 /cm.sup.3 and a thickness of 100 nm and the n-AlInAs layer 360 had a carrier concentration of 3.times.10.sup.17 /cm.sup.3 and a thickness of 500 nm.
In this FET, two two-dimensional electron gases 370 and 380 are formed near the interfaces of the undoped InGaAs layer 330 and the undoped InP layer 350. The electron gas dominantly travels on the side of the undoped InGaAs layer 330 in a low electric field. However, the electron gas dominantly travels on the side of the undoped InP layer 350 in a high electric field. Therefore, a large drain current is obtained, and a high driving capacity can be obtained.
In this FET, the present inventor conducted an experiment such that the n-InP layer 340 and the undoped InP layer 350 had a carrier concentration of 2.times.10.sup.18 /cm.sup.3 each and thicknesses of 30 nm and 10 nm, respectively, the n-AlInAs layer 360 had a carrier concentration of 2.times.10.sup.18 /cm.sup.3 and a thickness of 50 nm, and the undoped InGaAs layer 330 had a thickness of 10 nm. The present inventor found the following problems.
In this FET, the two two-dimensional electron gases 370 and 380 are formed and serve as channels. The two-dimensional electron gas 380 is farther spaced apart from the gate electrode 420 than the two-dimensional electron gas 370. For this reason, the drain current cutoff characteristics are degraded. In addition, the electron mobility must be set high, i.e., the source parasitic resistance must be reduced.
As described above, the conventional InP heterojunction field effect transistors pose problems on InP physical properties. No conventional InP heterojunction field effect transistor can sufficiently prevent degradation of InP physical properties.